1. Technical Field
The present disclosure relates to a semiconductor device, in particular, to a redundancy evaluation circuit for the semiconductor device.
2. Description of Related Art
Technological advances have permitted semiconductor integrated circuits to comprise significantly more circuit elements in a given silicon area. Reducing and eliminating defects in the circuit elements has, however, becomes increasingly more difficult with the increased number of circuit elements.
To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. The reduced size makes these circuit elements increasingly susceptible to defects caused by material impurities during fabrication. Nevertheless, the defects are identifiable upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. Therefore, elements of a redundancy circuit are provided on integrated circuits to reduce the number of scrapped integrated circuits. If an element of the primary circuit is determined to be defective, an element of the redundancy is substituted for the defective element of the primary circuit. Substantial reductions in scrap are achieved by using elements of the redundancy circuit without substantially increasing the cost of the integrated circuits. Since the elements of the redundancy circuit are used to replace the defective elements of the primary circuit, a redundancy evaluation circuit is thus used to evaluate whether a fuse status address signal hits a defective element address signal.
Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional redundancy evaluation circuit for a semiconductor device. The semiconductor device is for example a semiconductor memory device. The redundancy evaluation circuit 1 comprises (m+1) fuse boxes 11, (m+1) multiplexers 12, a decoder 13, a comparator 14, and an enable transistor ENT, wherein m is a bit number of a defective element address signal AD (i.e. the defective element address signal has m bits A1 through Am).
Input ends of each multiplexer 12 are connected to output ends of the corresponding fuse box 11, m output ends of the m multiplexers 12 are connected to m first input ends of the comparator 14 respectively, an output end of the other one multiplexer 12 is connected to an enable end of the comparator 14. The comparator 14 further comprises m second input ends for receiving the defective element address signal AD and an output end for outputting a redundancy enable signal HIT. Each multiplexer 12 has k control ends connected to k output ends of the decoder 13, and the decoder has n input ends for receiving a circuit block address signal BA, wherein k is the number of circuit blocks (such as the memory blocks), n is the number of bits associated with the circuit block address signal BA, and 2n-1<k≦2n. The enable transistor ENT is a NMOS transistor having a gate for receiving an enable signal EN, a source connected to a low reference voltage, such as a ground, and a drain connected to (m+1) reference ends of the (m+1) fuse boxes 11. Each of the fuse boxes 11 further has an input end for receiving a precharge signal PRE.
Each fuse box 11 comprises k redundant cells 111 through 11k. The redundant cell 111 comprises three PMOS transistors P11, P21, P31, a NMOS transistor N11, and a fuse f1. A gate of the PMOS transistor P11 is connected to the input end of the corresponding fuse box 11, and a gate of the PMOS transistor P21 is connected to drains of the PMOS transistor P31 and NMOS transistor N11. Sources of the PMOS transistors P11 through P31 receive a supply voltage, such as a power voltage VDD, drains of the PMOS transistors P11 and P21 are connected to one end of the fuse f1 and gates of the PMOS transistor P31 and the NMOS transistor N11. The other one end of the fuse f1 is connected to the reference end of the corresponding fuse box 11. A source of the NMOS transistor N11 is connected to the low reference voltage, such as the ground. The drains of the PMOS transistor P31 and the NMOS transistor N11 are connected to one of the m input ends associated with the corresponding multiplexer 12. It is noted that the PMOS transistor P21 forms a voltage keeper, and the PMOS transistor P31 and the NMOS transistor N11 form an inverter, such that the PMOS transistor P21, P31, and the NMOS transistor N11 form an inverted latch. By the similar manner, the redundant cell 11k comprises three PMOS transistors P1k, P2k, P3k, a NMOS transistor N1k, and a fuse fk, and the connection of the PMOS transistors P1k, P2k, P3k, the NMOS transistor N1k, and the fuse fk can be deduced from the above description of the redundant cell 111, thus omitting the redundant description.
A precharge signal PRE with a logic low level can be applied to the fuse boxes 11, such that nodes V1 through Vk of the redundant cells 111 through 11k in the fuse boxes 11 can be precharged, and the voltages of the nodes V1 through Vk are pulled up to the logic high level from the logic low level. Then, the precharge signal PRE goes to a logic high level from the logic low level, and the enable signal with the logic high level is applied to a gate of the enable transistor ENT. Thus, when the fuse f1 is melted (i.e. the corresponding redundant element is used to replace the defective element), the node V1 goes to the logic low level, and the corresponding input end of the corresponding multiplexer receive the logic low level; by contrast, when the fuse f1 is not melted (i.e. the corresponding redundant element is not used to replace the defective element), the node V1 maintains the logic high level, and the corresponding input end of the corresponding multiplexer receive the logic high level. By similar manner, the status of the fuse fk affects the level at the node Vk, and the redundant description is thus omitted.
The decoder 13 decodes a circuit block address signal BA to generate k selection signals to control the multiplexer 12, such that the multiplexers 12 can output inversions of the (m+1) levels of the selected (m+1) redundant cells of the (m+1) fuse boxes 11. For example, the k selection signals select the redundant cells 111, and thus the multiplexers 12 output the inversions of the (m+1) levels at the (m+1) nodes V1 to the comparator 14, wherein the inversions of the m levels at the m nodes V1 are output as the fuse status address signal FS, and the inversion of the other one level at the node V1 is output as the comparator enable signal CEN. When the comparator 14 is enabled by the comparator enable signal CEN, the comparator 14 compares the fuse status address signal FS with defective element address signal AD, so as to output the redundancy enable signal HIT.
It is noted that one of the fuse box 11 is used to store the information whether the circuit block has the defective element replaced by the redundant element, and the multiplexer 12 connected to this fuse box 11 outputs the comparator enable signal CEN to enable the comparator when the circuit block has the defective element replaced by the redundant element.
Referring to FIG. 2, FIG. 2 is a layout diagram of the conventional redundancy evaluation circuit. The redundancy evaluation circuit 1 in FIG. 1 needs several multiplexers 12, several PMOS transistors P11 through P1k, P21 through P2k, P31 through P3k, and several NMOS transistors N11 through N1k, and thus the layout area of the redundancy evaluation circuit 1 is large. Moreover, due to the structure of redundancy evaluation circuit 1, the fuses are layout on the two fuse regions F1 and F2 with a spacing W, and the peripheral elements (such as transistors and multiplexers) are also layout on the two peripheral regions PH1 and PH2 with a spacing W. The width of the fuse regions F1, F2 and the peripheral regions PH1, PH2 is 8.5 W, the height of the fuse regions F1 and F2 is 2.5 H, and the height of the peripheral regions PH1 and PH2 is 3 H. Thus the layout area of redundancy evaluation circuit 1 is 99 HW.